1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method of a semiconductor memory device, and more particularly relates to a semiconductor memory device including a select-line driving circuit for driving a select line and a manufacturing method of the semiconductor memory device.
2. Description of Related Art
In general, a DRAM (Dynamic Random Access Memory) has a hierarchical word line structure. Japanese Patent Application Laid-open No. 2006-270126 discloses an example of a DRAM configured by hierarchical word lines.
When hierarchical word lines are used, the word lines are hierarchized into main word lines that become high-order word lines and sub-word lines that become low-order word lines. Each sub-word line is connected to a main word line by a sub-word line driving circuit, and when a main word line driving circuit and the sub-word line driving circuit are activated based on a row address input from outside, a corresponding sub-word line is also activated.
Because many memory cells are connected to the sub-word lines, a transistor constituting the sub-word line driving circuit is required to have a relatively high driving capacity. Therefore, a current driving capacity needs to be secured by increasing a gate width of each transistor to some extent.
To secure a sufficient gate width, conventionally, an installation area of a sub-word line driving circuit takes a large length in an extending direction (a row direction) of sub-word lines. This is because sub-word line driving circuits are arranged along a layout direction (a column direction) of the sub-word lines, there is no room for a large length of the installation area of the sub-word line driving circuits in the layout direction of the sub-word lines.
However, when the installation area of the sub-word line driving circuits is long in the row direction, the entire size of the DRAM naturally becomes large. Therefore, it has been required to further decrease a size of the installation area in the row direction without degrading the performance of the sub-word line driving circuits.
Contact plugs that connect source/drain regions of each of transistors constituting the sub-word line driving circuit and the sub-word lines are formed by using a technique called a SAC (Self Aligned Contact) hole technique. According to this technique, an upper surface and a side surface of a gate electrode are first covered with a gate gap and a sidewall made of a silicon nitride film. The entire sense amplifier is covered on this with a silicon oxide film. The silicon oxide film is selectively etched by using a mask, thereby providing holes on the source/drain regions. Last, a conductive layer is embedded into the contact holes, thereby forming the contact plugs in self alignment.
The SAC hole technique has this name because a mask used for the above selective etching has holes for respective contacts.
However, the above technique has a problem in that a distance between a contact plug and a gate electrode becomes long. That is, because contact holes are very narrow holes, it takes some time before sufficient holes are formed. This is because it takes time for etchant to move in narrow holes. Accordingly, to prevent gate electrodes from being damaged, a gate gap and a sidewall need to have a large thickness to some extent. Consequently, a distance between a contact plug and a gate electrode becomes long corresponding to the large thickness.
When a distance between a contact plug and a gate electrode can be reduced, the inside of the sub-word line driving circuit can have high density, and a size of an installation area of the sub-word line driving circuit in the row direction can be reduced without degrading the performance of the sub-word line driving circuit.
The same can be also applied to other types of circuit that drives select lines (word lines are also one type of select lines) such as a column decoder that drives column select lines, not only to the sub-word line driving circuits.